NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 579

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13—Intel
Table 495. SDM—SDATA_IN Map Register (Sheet 2 of 2)
November 2007
Order Number: 300641-004US
Bits
Default Value:
1:0
3
2
Lockable:
Device:
®
Offset:
Last Codec Read Data
6300ESB ICH
Steer Enable (SE)
Input (LDI)
Reserved
31
NABMBAR + 80h
00h
No
Name
When set, the AC_SDIN lines are treated separately and not
OR’d together before being sent to the DMA engines. When
cleared, the AC_SDIN lines are OR’d together, and the
Microphone In 2 and PCM In 2 DMA engines are not available.
Reserved.
When a codec register is read, this indicates which AC_SDIN
the read data returned on. Software may use this to
determine how the codecs are mapped. The values are:
00
01
10
11
AC_SDIN0
AC_SDIN1
AC_SDIN2
Reserved
Power Well:
Description
Attribute:
Function:
Size:
5
Read/Write
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
RO
RO
579
DS