NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 238

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.19.2
Intel
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238
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6300ESB I/O Controller Hub
The Intel
checking (PEC) enabled or disabled. The actual PEC calculation and checking is
performed in software.The SMBus Host Controller logic may automatically append the
CRC byte when configured to do so.
The Slave Interface allows an external master to read from or write to the Intel
6300ESB ICH. Write cycles may be used to cause certain events or pass messages, and
the read cycles may be used to determine the state of various status bits. The Intel
6300ESB ICH’s internal Host Controller cannot access the Intel
internal Slave Interface.
The Intel
space, and consists of a transmit data path, and host controller. The transmit data path
provides the data flow logic needed to implement the seven different SMBus command
protocols and is controlled by the host controller. The Intel
controller logic is clocked by RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the new Host Notify command
(which is actually a received message).
The programming model of the host controller is combined into two portions: a PCI
configuration portion, and a system I/O mapped portion. All static configuration, such
as the I/O base address, is done through the PCI configuration space. Real-time
programming of the Host interface is done in system I/O space.
Host Controller
The SMBus Host Controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it will generate an SMI# or
interrupt, when enabled.
The host controller supports seven command protocols of the SMBus interface (see the
SMBus Specification): Quick Command, Send Byte, Receive Byte, Write Byte/Word,
Read Byte/Word, ProcessCall, Block Read, Block Write and Block Write-Block Read
process call.
The SMBus Host Controller requires that the various data and command fields be setup
for the type of command to be sent. When software sets the START bit, the SMBus Host
Controller will perform the requested transaction, and interrupt the processor (or
generate an SMI#) when the transaction is completed. Once a START command has
been issued, the values of the “active registers” (Host Control, Host Command,
Transmit Slave Address, Data 0, Data 1) should not be changed or read until the
interrupt status bit (INTR) has been set (indicating the completion of the command).
Any register values needed for computation purposes should be saved prior to issuing
of a new command, as the SMBus Host Controller will update all registers while
completing the new command.
Using the SMBus Host Controller to send commands to the Intel
SMBus slave port is supported.
The Intel
protocol, on the SMLink pins when in TCO compatible mode. Therefore, in order to be
fully compliant with the SMBus 2.0 specification (which requires the Host Notify cycle),
the SMLink and SMBus signals must be tied together externally. However, this
requirement to tie both SMLink and SMBus signals externally is not needed in advanced
TCO mode as the slave functionality is available on the SMBus pins.
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6300ESB ICH may perform SMBus messages with either packet error
6300ESB ICH SMBus logic exists in Device 31:Function 3 configuration
6300ESB ICH supports slave functionality, including the Host Notify
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6300ESB ICH SMBus
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Order Number: 300641-004US
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6300ESB ICH’s
6300ESB ICH's
Intel
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6300ESB ICH—5
November 2007
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