NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 600
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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14.2.8
Intel
DS
600
31:7
Bits
Bits
Default Value:
Default Value:
I/O Address:
2
1
0
I/O Address:
6
5
4
3
®
Table 524. x_CR—Control Register (Sheet 2 of 2)
Table 525. GLOB_CNT—Global Control Register (Sheet 1 of 2)
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: Reads across dWord boundaries are not supported.
Interrupt Enable (LVBIE)
Device:
Device:
Interrupt Enable (S1RE)
Interrupt Enable (S0RE)
ACLINK Shut Off (LSO)
Run/Pause Bus Master
AC_SDIN2 Interrupt
Reset Registers(RR)
AC_SDIN1 Resume
AC_SDIN0 Resume
Last Valid Buffer
Enable (S2RE)
GLOB_CNT—Global Control Register
Reserved
(RPBM)
29
MBAR + 0Bh (MICR),
MBAR + 1Bh (MOCR)
00h
No
Name
29
MBAR + 3Ch
00000000h
No
Name
This bit controls whether the completion of the last valid
buffer will cause an interrupt or not.
0 = Disable. Bit 2 in the Status register will still be set, but
1 = Enable
0 = Removes reset condition.
1 = Contents of all registers to be reset, except the interrupt
0 = Pause bus master operation. This results in all state
1 = Run. Bus master operation starts.
Reserved
0 = Disable.
1 = Enable an interrupt to occur when the codec on
0 = Disable.
1 = Enable an interrupt to occur when the codec on
0 = Disable.
1 = Enable an interrupt to occur when the codec on
0 = Normal operation.
1 = Controller disables all outputs which will be pulled low by
the interrupt will not occur.
enable bits (bit 4,3,2 of this register). Software must set
this bit. It must be set only when the Run/Pause bit is
cleared. Setting it when the Run bit is set will cause
undefined consequences. This bit is self-clearing
(software needs not clear it).
information being retained (i.e., master mode operation
may be stopped and then resumed).
AC_SDIN[2] causes a resume event on the AC-link.
AC_SDIN[1] causes a resume event on the AC-link.
AC_SDIN[0] causes a resume event on the AC-link.
internal pull down resistors.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read/Write
8-bit
Core
5
Read/Write
32-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—14
November 2007
(special)
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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