NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 629

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16—Intel
16.4.21 Offset Base + 0Ch: Reload Register
Table 556. Offset Base + 0Ch: Reload Register
16.5
16.5.1
16.5.2
November 2007
Order Number: 300641-004US
NOTE: The reload sequence is only necessary for the Reload register and Preload_Value registers and is not
15:1
Bits
Default Value:
7:0
0
9
8
Lockable:
used in Free Running mode.
Device:
®
Offset:
6300ESB ICH
WDT_TIMEOUT
WDT_RELOAD
Theory Of Operation
The WDT_TIMEOUT bit is set to a ‘1’ when the WDT 35-bit down counter reaches zero
for the second time in a row. The WDT_TOUT# pin is then toggled LOW by the WDT
from the Intel
the appropriate external signal. When WDT_TOUT_CNF is a ’1’ the WDT toggles
WDT_TOUT# again when the next timeout occurs. Otherwise, WDT_TOUT# is driven
low until the system is reset or power is cycled.
Register Unlocking Sequence
The register unlocking sequence is necessary whenever writing to the RELOAD register
or either PRELOAD_VALUE registers. The host must write a sequence of two writes to
offset BAR + 0Ch before attempting to write to either the WDT_RELOAD and
WDT_TIMEOUT bits of the RELOAD register or the PRELOAD_VALUE registers. The first
writes are 80 and 86, in that order, to offset BAR + 0Ch. The next write will be to the
proper register (e.g., RELOAD, PRELOAD_VALUE_1, PRELOAD_VALUE_2)
RTC Well and WDT_TOUT# Functionality
Reserved
Reserved
29
Base + 0Ch
0000h
No
Name
®
6300ESB ICH. The board designer should attach the WDT_TOUT# to
Reserved.
This bit resides in the RTC Well and its value is not lost if the
host resets the system. It is set to '1' if the host fails to reset
the WDT before the 35-bit Down-Counter reaches zero for the
second time in a row. This bit is cleared by performing the
Register Unlocking Sequence followed by a '1' to this bit.
0 = Normal (Default).
1 = System has become unstable.
NOTE: In free running mode this bit is set every time the
To prevent a timeout, the host must perform the Register
Unlocking Sequence followed by a '1' to this bit (See Register
Unlocking Sequence).
NOTE: Refer to Register Unlocking Sequence for details on
Reserved.
down counter reaches zero.
how to write to this bit.
Power Well:
Description
Attribute:
Function:
Size:
4
Read-Write
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
RO
W
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