NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 575

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13—Intel
November 2007
Order Number: 300641-004US
31:3
23:2
21:2
19:1
Bits
Default Value:
29
28
27
26
25
24
17
I/O Address:
0
2
0
8
Table 493. GLOB_STA—Global Status Register (Sheet 1 of 3)
Lockable:
Device:
Multichannel Capabilities
Bit Clock Stopped (BCS)
®
AC_SDIN2 Codec Ready
6300ESB ICH
Sample Capabilities
AC_SDIN2 Resume
PCM In 2 Interrupt
Interrupt (M2INT)
S/PDIF Interrupt
Interrupt (S2RI)
Microphone 2 In
Reserved
Reserved
(SPINT)
(P2INT)
(S2CR)
31
NABMBAR + 30h
00700000h
No
Name
MD3
Reserved.
This bit indicates that a resume event occurred on
AC_SDIN[2].
0 = Cleared by writing a ’1’ to this bit position.
1 = Resume event occurred.
This bit is not affected by D3
Reflects the state of the codec ready bit in AC_SDIN[2]. Bus
masters ignore the condition of the codec ready bits, so
software must check this bit before starting the bus masters.
Once the codec is “ready”, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
Indicates that the bit clock is not running. This bit is set when
the Intel
transition on BIT_CLK for four consecutive PCI clocks. It is
cleared when a transition is found on BIT_CLK.
Indicates that the S/PDIF out channel interrupt status bits
have been set. When the specific status bit is cleared, this bit
will be cleared.
Indicates that one of the PCM In 2 channel status bits have
been set. When the specific status bit is cleared, this bit will
be cleared.
Indicates that one of the Mic in channel interrupts status bits
has been set. When the specific status bit is cleared, this bit
will be cleared.
Indicates the capability to support greater than 16-bit audio.
00 = Reserved
01 = 16 and 20-bit Audio supported (Intel
value)
10 = Reserved
11 = Reserved
Indicates the capability to support more 4 and 6 channels on
PCM Out.
Reserved.
Power down semaphore for Modem. This bit exists in the
suspend well and maintains context across power states
(except G3). The bit has no hardware function. It is used by
software in conjunction with the AD3 bit to coordinate the
entry of the two codecs into D3 state.
This bit is not affected by D3
®
6300ESB ICH detects that there has been no
Power Well:
Description
Attribute:
Function:
HOT
HOT
Size:
to D0 Reset.
to D0 Reset.
5
Read-Only, Read/Write, Read/Write Clear
32-bit
Core
®
6300ESB ICH
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/W
RO
RO
RO
RO
RO
RO
RO
575
DS