NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 292

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7.1.8
Table 154. Offset 0Dh: PMLT—Primary Master Latency Timer Register (HUB-PCI—
7.1.9
Table 155. Offset 0Eh: HEADTYP—Header Type Register (HUB-PCI—D30:F0)
7.1.10
Table 156. Offset 18h: PBUS_NUM—Primary Bus Number Register (HUB-PCI—
Intel
DS
292
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:3
2:0
6:0
7:0
7
®
6300ESB I/O Controller Hub
Note: This register does not apply to Hub Interface.
Device:
Device:
Device:
Offset:
Offset:
Offset:
Master Latency Count
Multi-Function Device
Primary Bus Number
Header Type
Offset 0Dh: PMLT—Primary Master Latency Timer
Register (HUB-PCI—D30:F0)
D30:F0)
Offset 0Eh: HEADTYP—Header Type Register
(HUB-PCI—D30:F0)
Offset 18h: PBUS_NUM—Primary Bus Number
Register (HUB-PCI—D30:F0)
D30:F0)
Reserved
30
0Dh
00h
Name
30
0Eh
01h
Name
30
18h
00h
Name
Not implemented.
Reserved.
This bit is ‘0’ to indicate a single function device.
8-bit field identifies the header layout of the configuration
space, which is a PCI-to-PCI bridge in this case.
This field indicates the bus number of the Hub Interface and
is hardwired to 00h.
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
0
Read-Only
8-bit
0
Read-Only
8-bit
0
Read-Only
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—7
November 2007
Access
Access
Access
RO
RO
RO