NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 352

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.2.6
Table 225. DMA_WRSMSK—DMA Write Single Mask Register
8.2.7
Table 226. DMACH_MODE—DMA Channel Mode Register (Sheet 1 of 2)
Intel
DS
352
Bits
Bits
Default Value:
Default Value:
7:3
1:0
7:6
I/O Address:
2
I/O Address:
5
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
Device:
Channel Mask Select
DMA Channel Select
Address Increment/
DMA Transfer Mode
Decrement Select
DMA_WRSMSK—DMA Write Single Mask Register
DMACH_MODE—DMA Channel Mode Register
Reserved
31
Ch. #0-3 = 0Ah
Ch. #4-7 = D4h
0000 01xx
No
Name
31
Ch. #0-3 = 0Bh
Ch. #4-7 = D6h
0000 00xx
No
Name
Reserved. Must be zero.
0 = Enable DREQ for the selected channel. The channel is
1 = Disable DREQ for the selected channel.
These bits select the DMA Channel Mode Register to program.
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
Each DMA channel may be programmed in one of four
different modes:
00 = Demand mode
01 = Single mode
10 = Reserved
11 = Cascade mode
This bit controls address increment/decrement during DMA
transfers.
0 = Address increment. (default after part reset or Master
1 = Address decrement.
selected through bits [1:0]. Therefore, only one channel
may be masked / unmasked at a time.
Clear)
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Write-Only
8-bit
Core
0
Write-Only
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
Access
WO
WO
WO
WO