NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 33

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
Tables
November 2007
Order Number: 300641-004US
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Industry Specifications.............................................................................................. 49
Intel
Hub Interface Signals ............................................................................................... 55
Firmware Hub Interface Signals ................................................................................. 56
PCI Interface Signals ................................................................................................ 57
PCI-X Interface Signals ............................................................................................. 60
SATA Interface Signals ............................................................................................. 64
IDE Interface Signals................................................................................................ 64
LPC Interface Signals................................................................................................ 66
Interrupt Signals...................................................................................................... 66
USB Interface Signals ............................................................................................... 67
Power Management Interface Signals.......................................................................... 68
CPU Interface Signals ............................................................................................... 69
SM Bus Interface Signals .......................................................................................... 71
System Management Interface Signals........................................................................ 71
Real Time Clock Interface.......................................................................................... 71
Other Clocks ........................................................................................................... 72
Miscellaneous Signals ............................................................................................... 72
AC’97 Link Signals.................................................................................................... 73
Universal Asynchronous Receive and Transmit (UART0, 1) ............................................. 73
General Purpose I/O Signals ...................................................................................... 75
Power and Ground Signals......................................................................................... 76
Functional Strap Definitions ....................................................................................... 77
Revision and Device ID Table..................................................................................... 78
Intel
Integrated Pull-Up and Pull-Down Resistors ................................................................. 80
IDE Series Termination Resistors................................................................................ 81
Power Plane and States for Output and I/O Signal for Desktop Configurations .................. 83
Power Plane for Input Signals for Desktop Configurations .............................................. 90
Type 0 Configuration Cycle Device Number Translation ................................................. 96
LPC Cycle Types Supported ....................................................................................... 98
Start Field Bit Definitions .......................................................................................... 98
Cycle Type Bit Definitions .......................................................................................... 99
Transfer Size Bit Definition ........................................................................................ 99
SYNC Bit Definition................................................................................................... 99
Response to Sync Failures ....................................................................................... 100
Fixed Priority ......................................................................................................... 104
DMA Transfer Size.................................................................................................. 105
Address Shifting in 16-bit I/O DMA Transfers ............................................................. 105
Counter Operating Modes ........................................................................................ 111
Interrupt Controller Core Connections ....................................................................... 113
Interrupt Status Registers ....................................................................................... 114
Content of Interrupt Vector Byte .............................................................................. 115
Interrupt Mapping in Non-APIC ................................................................................ 123
APIC Interrupt Mapping, APIC0 Agent ....................................................................... 124
APIC Interrupt Mapping, APIC1 Agent ....................................................................... 125
Arbitration Cycles................................................................................................... 126
APIC Message Formats ........................................................................................... 126
EOI Message ......................................................................................................... 127
Short Message....................................................................................................... 128
APIC Bus Status Cycle Definition .............................................................................. 129
Lowest Priority Message (Without Focus Processor)..................................................... 130
Remote Read Message ............................................................................................ 131
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6300ESB ICH Clock Domains............................................................................ 53
6300ESB I/O Controller Hub Power Planes ......................................................... 79
6300ESB ICH
Intel
®
6300ESB I/O Controller Hub
DS
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