NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 511

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
Table 412. Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB EHCI Command
November 2007
Order Number: 300641-004US
NOTE: The Command Register indicates the command to be executed by the serial bus host controller. Writing
Bits
Default Value:
1
0
to the register causes a command to be executed.
Device:
®
Offset:
Host Controller Reset
6300ESB ICH
Run/Stop (RS)
(HCRESET)
Register (Sheet 3 of 3)
29
CAPLENGTH + 00-03h
00080000h
Name
This control bit is used by software to reset the host
controller. The effects of this on Root Hub registers are similar
to a Chip Hardware Reset (i.e., RSMRST# assertion and
PWROK deassertion on the Intel
When software writes a ’1’ to this bit, the Host Controller
resets its internal pipelines, timers, counters, state machines,
etc. to their initial value. Any transaction currently in progress
on USB is immediately terminated. A USB reset is not driven
on downstream ports.
NOTE: PCI Configuration registers and Host Controller
All operational registers, including port registers and port
state machines are set to their initial values. Port ownership
reverts to the companion host controller(s), with the side
effects described in the EHCI spec. Software must re-initialize
the host controller in order to return the host controller to an
operational state.
This bit is set to ’0’ by the Host Controller when the reset
process is complete. Software cannot terminate the reset
process early by writing a ’0’ to this register.
Software should not set this bit to a ’1’ when the HCHalted bit
in the USBSTS register is a ’0’. Attempting to reset an actively
running host controller will result in undefined behavior. This
reset can be used to leave EHCI port test modes.
Default 0b. 1=Run. 0=Stop. When set to a 1, the Host
Controller proceeds with execution of the schedule. The Host
Controller continues execution as long as this bit is set. When
this bit is set to 0, the Host Controller completes the current
transaction on the USB and then halts. The HC Halted bit in
the status register indicates when the Host Controller has
finished the transaction and has entered the stopped state.
Software should not write a ’1’ to this field unless the host
controller is in the Halted state (i.e., HCHalted in the USBSTS
register is a ’1’). The Halted bit is cleared immediately when
the Run bit is set.
The following table explains how the different combinations of
Run and Halted should be interpreted:
Run/Stop
0
0
1
1
Memory read cycles initiated by the EHC that receive any
status other than Successful will result in this bit being
cleared.
Capability Registers are not effected by this reset.
Halted
0
1
0
1
Interpretation
Valid - in the process of halting
Valid - halted
Valid - running
immediately.
Invalid - the HCHalted bit clears
Description
Attribute:
Function:
Size:
®
6300ESB ICH).
7
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
511
DS