NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 99

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.2.1.2
Table 33.
5.2.1.3
Table 34.
5.2.1.4
Table 35.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Cycle Type/Direction (CYCTYPE + DIR)
The Intel
bus master cycles must also drive bit 0 to 0. The following table shows the valid bit
encodings:
Cycle Type Bit Definitions
SIZE
Bits[3:2] are reserved. The Intel
Peripherals running bus master cycles are also supposed to drive 00 for bits 3:2,
however, the Intel
follows:
Transfer Size Bit Definition
SYNC
Valid values for the SYNC field are:
SYNC Bit Definition (Sheet 1 of 2)
NOTE: All other combinations are Reserved.
Bits[3:2
Bits[1:0]
Bits[3:0]
00
00
01
01
10
10
11
0000
0101
]
00
01
10
11
®
6300ESB ICH will always drive bit 0 of this field to zero. Peripherals running
Bit[1]
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel
peripheral running a bus master cycle drives this combination, the Intel
6300ESB ICH may abort the transfer.
32-bit transfer (4 bytes)
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA
request deassertion and no more transfers desired for that channel.
Short Wait: Part indicating wait-states. For bus master cycles, the Intel
6300ESB ICH will not use this encoding. It will instead use the Long Wait
encoding (see next encoding below).
0
1
0
1
0
1
x
®
6300ESB ICH will ignore those bits. Bits[1:0] are encoded as
I/O Read
I/O Write
Memory Read
Memory Write
DMA Read
DMA Write
Reserved. When a peripheral performing a bus master cycle generates
this value, the Intel
®
®
6300ESB ICH will never drive this combination. When a
6300ESB ICH will always drive them to 00.
®
6300ESB ICH will abort the cycle.
Indication
Size
Definition
Intel
®
6300ESB I/O Controller Hub
®
®
DS
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