NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 498

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 401. Offset 62 - 63h: Port Wake Capability
11.1.24 Offset 64 - 65h: Classic USB Override
Intel
DS
498
15:5
Bits
Default Value:
4:1
0
®
6300ESB I/O Controller Hub
Note: This 16-bit register provides a bit corresponding to each of the ports on the EHCI host
Note: EHCI test modes will not work on a port that has been overridden by this register.
Device:
Port Wake Implemented
Port Wake Up Capability
Offset:
controller. When a bit is set to ‘1’, the corresponding USB port is routed to the classic
(UHCI) host controller and will operate using only the classic signaling rates. The
feature is implemented with the following requirements:
Reserved
•
•
•
•
•
29
62 - 63h
001Fh
Name
Mask
The associated Port Owner bit does not reflect the value in this new Override
register. This guarantees compatibility with EHCI drivers.
The associated Port Owner bit does not reflect the value in this new Override
register. This guarantees compatibility with EHCI drivers.
BIOS must only write to this register during initialization (while the Configured Flag
is ‘0’).
The register is implemented in the Suspend well to maintain port-routing when the
core power goes down
When a ‘1’ is present in the Override register, the classic controller operates the
port regardless of the EHCI port routing logic. The corresponding EHCI port will
always appear disconnected in this mode.
Reserved.
Bit positions 1 through 4 correspond to a physical port
implemented on this host controller. For example, bit position
1 corresponds to port 0, position 2 port 1, position 3 port 2,
position 4 port 3.
A ’1’ in bit 0 indicates that this register is implemented to
software.
Description
Attribute:
Function:
Size:
7
Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
RW
RW