NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 798
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
Lead Free Status / RoHS Status
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Table 714. Clock Timings (Sheet 3 of 3)
Intel
DS
798
NOTES:
10.All PCI-X devices must be capable of operating in conventional PCI 33 mode and optionally are capable of
1. CLK48 is a 48 MHz clock that expects a 40/60% duty cycle.
2. CLK48 is a pass-thru clock that is not altered by the Intel
3. The maximum high time (t18 Max) provide a simple ensured method for devices to detect bus idle
4. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
5. This specification includes pin-to-pin skew from the clock generator as well as board skew.
6. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
7. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum limits
8. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in
9. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system
Sym
specification is required for USB 2.0 compliance and is affected by external elements such as the clock
generator and the system board.
conditions.
except while RST# is asserted.
Figure
jitter.
conventional PCI 66 mode.
®
6300ESB I/O Controller Hub
43.
Parameter
®
6300ESB ICH. This frequency tolerance
Min
Max
Unit
Order Number: 300641-004US
Intel
Notes
®
6300ESB ICH—22
November 2007
Figure
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