NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 134

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.7.7.2
5.7.7.3
5.7.7.4
5.7.7.5
Table 54.
:
Intel
DS
134
®
6300ESB I/O Controller Hub
Edge-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt.
Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt. When the interrupt is still active after an EOI, another “Assert Message”
is sent to indicate that the interrupt is still active.
Registers Associated with Processor System Bus Interrupt
Delivery
Capabilities Indication
The capability to support Processor System Bus interrupt delivery will be indicated
through ACPI configuration techniques. This involves the BIOS creating a data structure
that gets reported to the ACPI configuration software.
DT Bit in the Boot Configuration Register
This enables the Intel
ignored when the APIC mode is not enabled.
Interrupt Message Format
The Intel
32-bit memory write cycle. It uses the formats shown in
Address and Data.
The local APIC (in the processor) has a delivery mode option to interpret Processor
System Bus messages as a SMI in which case the processor treats the incoming
interrupt as a SMI instead of as an interrupt. This does not mean that the Intel
6300ESB ICH has any way to have a SMI source from the Intel
management logic cause the I/OAPIC to send an SMI message (there is no way to do
this). The Intel
which do not include SMI, NMI or INIT. This means that in IA32/IA64 based platforms,
Processor System Bus interrupt message format delivery modes 010 (SMI/PMI), 100
(NMI), and 101 (INIT) as indicated in this section, must not be used and is not
supported. Only the hardware pin connection is supported by the Intel
Interrupt Message Address Format (Sheet 1 of 2)
31:20
19:12
11:4
Bit
Will always be FEEh
Destination ID: This will be the same as bits 63:56 of the I/O Redirection Table entry
for the interrupt associated with this message.
Extended Destination ID: This will be the same as bits 55:48 of the I/O Redirection
Table entry for the interrupt associated with this message.
®
6300ESB ICH writes the message to PCI (and to the Host Controller) as a
®
6300ESB ICH’s I/OAPIC may only send interrupts due to interrupts
®
6300ESB ICH to deliver interrupts as memory writes. This bit is
Description
Table 54
®
Order Number: 300641-004US
6300ESB ICH power
and
Intel
®
Table 55
®
6300ESB ICH.
6300ESB ICH—5
November 2007
®
for the