NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 447

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
9.1.19
9.1.20
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:3
2:0
Table 341. Offset 3Dh: INTR_PN—Interrupt Pin Register (IDE—D31:F1)
®
Note: This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
Device:
Offset:
6300ESB ICH
Interrupt Pi
Offset 3Dh: INTR_PN—Interrupt Pin Register
(IDE—D31:F1)
IDE_TIM—IDE Timing Register (IDE—D31:F1)
transfers. It also controls operation of the buffer for PIO transfers.
Reserved
31
3Dh
01h
Name
Reserved.
The value of 01h indicates to “software” that the Intel
6300ESB ICH will drive INTA#. Note that this is only used in
native mode. Also note that the routing to the internal
interrupt controller does not necessarily relate to the value in
this register. The IDE interrupt is in fact routed to PIRQ[C]#
(IRQ18 in APIC mode).
Description
Attribute:
Function:
Size:
1
Read-Only
8-bit
Intel
®
®
6300ESB I/O Controller Hub
Access
RO
447
DS