NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 664

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.6.1.14Offset 20: MBL—Memory Base and Limit
Intel
DS
664
31:2
19:1
15:0
03:0
Bits
Bits
3:0
5
4
0
6
4
0
®
Table 596. Offset 1E: SSTS—Secondary Status (Sheet 2 of 2)
Table 597. Offset 20: MBL—Memory Base and Limit
6300ESB I/O Controller Hub
Note: Defines the base and limit, aligned to a 1 Mbyte boundary, of the memory area of the
Note: Accesses from PCI-X that are outside the ranges specified are forwarded to the Hub
Device
Device
Limit (ML)
Base (MB)
Assertion
Offset
Reserved
Offset
Reserved
Reserved
Capable
Memory
Memory
66 MHz
PERR#
Name
Detect
Name
(C66)
bridge. Accesses from the Hub Interface that are within the ranges specified in this
register are sent to PCI-X when the memory space enable bit is set.
Interface when the bus master enable bit is set.
28
1E
28
20
Indicates the secondary interface of the bridge is 66 MHz
capable.
This bit is set by hardware whenever the PERR# pin is
asserted on the rising edge of PCI-X clock. This includes cases
in which the chipset is the agent driving PERR#. It remains
asserted until cleared by software writing a ‘1’ to this
location. When enabled by the PERR#-to-SERR# Enable bit
(in the Bridge Control register), a ‘1’ in this bit can generate
an internal SERR# and be a source for the NMI logic.
Reserved.
These bits are compared with bits 31:20 of the incoming
address to determine the upper 1 Mbyte aligned value
(exclusive) of the range. The incoming address must be less
than or equal to this value.
Reserved.
These bits are compared with bits 31:20 of the incoming
address to determine the lower 1 Mbyte aligned value
(inclusive) of the range. The incoming address must be
greater than or equal to this value.
Reserved.
Description
Description
Attribute:
Attribute:
Function
Function
Size:
Size:
0
Read/Write Clear
16-bit
0
Read/Write
32-bit
Order Number: 300641-004US
Reset
Value
Reset
Value
000h
000h
00h
Intel
0h
0h
1
®
6300ESB ICH—18
November 2007
Access
Access
R/WC
R/W
R/W
RO
RO
RO
RO