NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 377

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.6.2.1
Table 262. RTC_REGD—Register D (Flag Register)
November 2007
Order Number: 300641-004US
Bits
Default Value:
6:4
3:0
7
RTC Index:
Lockable:
®
Note: This register is used for general configuration of the RTC functions. None of the bits are
Device:
UIP: Update In Progress
DV[2:0]: Division Chain
6300ESB ICH
RS[3:0] Rate Select
RTC_REGA—Register A
affected by RSMRST# or any other Intel
31
0A
Undefined
No
Name
Select
This bit may be monitored as a status flag.
0 = The update cycle will not start for at least 492 µs. The
1 = The update is soon to occur or is in progress.
These three bits control the divider chain for the oscillator,
and are not affected by RSMRST# or any other reset signal.
DV[2] corresponds to bit 6.
010 = Normal Operation
11X = Divider Reset
101 = Bypass 15 stages (test mode only)
100 = Bypass 10 stages (test mode only)
011 = Bypass 5 stages (test mode only)
001 = Invalid
000 = Invalid
Selects one of 13 taps of the 15 stage divider chain. The
selected tap may generate a periodic interrupt when the PIE
bit is set in Register B. Otherwise this tap will set the PF flag
of Register C. When the periodic interrupt is not to be used,
these bits should all be set to zero. RS3 corresponds to bit 3.
0000 = Interrupt never toggles
0001 = 3.90625 ms
0010 = 7.8125 ms
0011 = 122.070 µs
0100 = 244.141 µs
0101 = 488.281 µs
0110 = 976.5625 µs
0111 = 1.953125 ms
1000 = 3.90625 ms
1001 = 7.8125 ms
1010 = 15.625 ms
1011 = 31.25 ms
1100 = 62.5 ms
1101 = 125 ms
1110 = 250 ms
1111= 500 ms
time, calendar, and alarm information in RAM is always
available when the UIP bit is 0.
Power Well:
Description
Attribute:
®
Function:
6300ESB ICH reset signal.
Size:
0
Read/Write
8-bit
RTC
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
377
DS