NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 171

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.12.3.4 Handling an Intruder
5.12.3.5 Detecting Improper FWH Programming
5.12.3.6 Handling an ECC Error or Other Memory Error
November 2007
Order Number: 300641-004US
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Note: The INTRD_DET bit resides in the Intel
Note: When the INTRUDER# signal is still active when software attempts to clear the
6300ESB ICH
The exact recovery algorithm will be system-specific.
When after the TIMEOUT SMI is generated, and the TCO timer again reaches 0, and
reboots are enabled, the System Management logic will reset (and reboot) the system.
This would be in the case where the processor or system is locked up. During every
boot, BIOS should read the SECOND_TO_STS bit in the TCO_STS register to see if this
is normal boot or a reboot due to the timeout.
The Intel
switch that is activated by the system’s case being open. This input has a two RTC clock
debounce. When INTRUDER# goes active (after the debouncer), this will set the
INTRD_DET bit in the TCO_STS register. The INTRD_SEL bits in the TCO_CNT register
may enable the Intel
interrupt handler may then cause a transition to the S5 state by writing to the SLP_EN
bit.
The software may also directly read the status of the INTRUDER# signal (high or low)
by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a
GPI when the intruder function is not required.
When the INTRUDER# signal goes inactive some point after the INTRD_DET bit is
written as a 1, the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes
inactive. Note that this is slightly different than a classic sticky bit, since most sticky
bits would remain active indefinitely when the signal goes active and would
immediately go inactive when a 1 is written to the bit.
cleared synchronously with the RTC clock. Thus, when software attempts to clear
INTRD_DET (by writing a ‘1’ to the bit location) there may be as much as two RTC
clocks (about 65 µs) delay before the bit is actually cleared. Also, the INTRUDER#
signal should be asserted for a minimum of 1 ms in order to ensure that the
INTRD_DET bit will be set.
INTRD_DET bit, the bit will remain set and the SMI will be generated again
immediately. The SMI handler may clear the INTRD_SEL bits to avoid further SMIs.
However, when the INTRUDER# signal goes inactive and then active again, there will
not be further SMIs, since the INTRD_SEL bits would select that no SMI# be generated.
The Intel
will result in the first instruction fetched to have a value of FFh. When this occurs, the
Intel
the Heartbeat and Event reporting via an LAN Controller.
The Host Controller provides a message to indicate that it would like to cause an SMI#,
SCI, SERR#, or NMI. The software must check the Host Controller as to the exact cause
of the error.
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b. Write to the TCO_RLD register to reload the timer to make sure the TCO timer
c. Attempt to recover. May need to periodically reload the TCO timer.
6300ESB ICH will set the BAD_BIOS bit, which may then be reported through
does not reach 0 again.
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6300ESB ICH has an input signal, INTRUDER#, that may be attached to a
6300ESB ICH may detect the case where the FWH is not programmed. This
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6300ESB ICH to cause an SMI# or interrupt. The BIOS or
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6300ESB ICH’s RTC well, and is set and
Intel
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6300ESB I/O Controller Hub
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