NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 753

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20—Intel
November 2007
Order Number: 300641-004US
Bits
Default Value:
5:4
3:2
1:0
Table 682. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
Device:
®
Offset:
Primary Drive 1 Cycle
Primary Drive 0 Cycle
6300ESB ICH
Time (PCT1)
Time (PCT0)
(SATA–D31:F2) (Sheet 2 of 2)
Reserved
31
4A-4Bh
0000h
Name
For Ultra ATA mode, the setting of these bits determines the
minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
PCB1 = 0 (33MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = ’1’ (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = ’1’ (133MHz clk)
01 = CT 3 clks, RP 16 clks
00 = Reserved
10 = Reserved
11 = Reserved
Reserved.
For Ultra ATA mode, the setting of these bits determines the
minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
PCB1 = 0 (33MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = ’1’ (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = ’1’ (133MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Description
Attribute:
Function:
Size:
2
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
753
DS