NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 655

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.6.1.3 Offset 04: CMD—Command
November 2007
Order Number: 300641-004US
15:1
Bits
09
08
07
06
05
04
03
0
Table 586. Offset 04: CMD—Command (Sheet 1 of 2)
VGA Palette
Parity Error
®
(VGA_PSE)
Fast Back-
Wait Cycle
Device
Invalidate
Write and
Response
Offset
Reserved
Memory
to-back
(MWIE)
Control
6300ESB ICH
SERR#
(PERE)
Special
Enable
Enable
Enable
Enable
Enable
Name
enable
(WCC)
Snoop
(SCE)
(FBE)
(SEE)
Cycle
This controls how the device behaves on the primary interface and is the same as all
other devices, with the exception of the VGA Palette Snoop bit. As this component is a
bridge, additional command information is located in a separate register called “Bridge
Control” located at offset 3E.
28
04
Reserved.
This bit has no meaning on the Hub Interface. It is hardwired
to '0'.
Controls the enable for assertion of SERR# (via NMI/SMI#)
when the SSE bit (D28:F0:Offset 06h, bit 14) is set. See
Section 5.1.4
0 = SERR# disabled
1 = SERR# enabled
Reserved.
Controls the Intel
error is detected on the Hub Interface.
0 = The Intel
1 = The Intel
NOTE: The Hub Interface Parity Unsupported bit
Reserved.
The Intel
and invalidate transactions, as the Hub Interface does not
have a corresponding transfer type.
Reserved.
Interface.
Interface and sets the DPD bit in the status register.
(D30:F0:40h:bit 20) must be cleared for the PER bit
to have any effect.
®
6300ESB ICH does not generate memory write
®
®
for more details on this bit.
6300ESB ICH ignores these errors on the Hub
6300ESB ICH reports these errors on the Hub
®
6300ESB ICH's response when a parity
Description
Attribute:
Function
Size:
0
Read/Write
16-bit
Intel
®
Reset
Value
6300ESB I/O Controller Hub
00h
0
0
0
0
0
0
0
Access
R/W
R/W
RO
RO
RO
RO
RO
RO
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