NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 325

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.1.19
Table 199. Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—
8.1.20
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:3
2
1
0
Lockable:
®
Note: This register configures the Intel
Note: This register configures the Intel
Device:
Offset:
on Delayed Transaction
SERR_RTA_EN: SERR#
SERR_DTT_EN: SERR#
6300ESB ICH
on Received Target
Timeout Enable
Abort Enable
Offset 88h: D31_ERR_CFG—Device 31 Error Config
Register (LPC I/F—D31:F0)
system errors. The actual assertion of SERR# is enabled through the PCI Command
register.
D31:F0)
Offset 8Ah: D31_ERR_STS—Device 31 Error Status
Register (LPC I/F—D31:F0)
system errors. The actual assertion of SERR# is enabled through the PCI Command
register.
Reserved
Reserved
31
88h
00h
No
Name
Reserved.
0 = Disable. No SERR# assertion on Received Target Abort.
1 = The Intel
0 = Disable. No SERR# assertion on Delayed Transaction
1 = The Intel
Reserved.
SERR_RTA is set and if SERR_EN is set.
Timeout.
SERR_DTT bit is set and if SERR_EN is set.
®
®
6300ESB ICH will generate SERR# if the
6300ESB ICH will generate SERR# if the
®
®
6300ESB ICH’s Device 31 responses to various
6300ESB ICH’s Device 31 responses to various
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
325
DS