NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 599

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14—Intel
14.2.6
14.2.7
November 2007
Order Number: 300641-004US
15:0
Bits
Bits
Default Value:
Default Value:
7:5
I/O Address:
I/O Address:
4
3
Table 523. x_PIV—Prefetch Index Value Register
Table 524. x_CR—Control Register (Sheet 1 of 2)
Lockable:
Lockable:
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
Device:
Device:
Interrupt On Completion
®
6300ESB ICH
FIFO Error Interrupt
Position In Current
Enable (IOCE)
Enable (FEIE)
Buffer[15:0]
x_PIV—Prefetch Index Value Register
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Ah. Reads across dWord boundaries are not supported.
x_CR—Control Register
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Bh. Reads across dWord boundaries are not supported.
Reserved
29
MBAR + 0Ah (MIPIV),
MBAR + 1Ah (MOPIV)
00h
No
Name
29
MBAR + 0Bh (MICR),
MBAR + 1Bh (MOCR)
00h
No
Name
These bits represent the number of samples left to be
processed in the current buffer.
Reserved.
This bit controls whether or not an interrupt occurs when a
buffer completes with the IOC bit set in its descriptor.
0 = Disable
1 = Enable
This bit controls whether the occurrence of a FIFO error will
cause an interrupt or not.
0 = Disable. Bit 4 in the Status Register will be set, but the
1 = Enable. Interrupt will occur.
interrupt will not occur.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read-Only
8-bit
Core
5
Read/Write
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
RO
599
DS