NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 59

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3—Intel
Table 5.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
PCI Interface Signals (Sheet 3 of 3)
PLOCK#
SERR#
PME#
Signal
Name
Type
I/O
I/OD
I/OD
PCI Lock: Indicates an exclusive bus operation and may require multiple
transactions to complete. The Intel
when it is doing non-exclusive transactions on PCI. PLOCK# is ignored
when PCI masters are granted the bus.
System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
Intel
Implemented as I/O open drain. This allows the Intel
drive these signals due to internal sources.
PCI Power Management Event: Driven by PCI peripherals to wake the
system from low-power states S1-S5. If can also cause an SCI from the
S0 state. Note that in some cases the Intel
PME# active (low) due to an internal wake event. It will not drive PME#
high (but it may be pulled up using the internal pull-up resistor).
NOTE: PME# is in the Resume power plane and has an internal pull-up
NOTE: PME# is also used in the PCI-X segment.
®
6300ESB ICH can be programmed to generate an NMI or SMI#.
resistor.
Description
®
6300ESB ICH ICH asserts PLOCK#
®
Intel
6300ESB ICH may drive
®
6300ESB I/O Controller Hub
®
6300ESB ICH to
DS
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