NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 689

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.7.9.1 Data Parity Errors
18.7.9.1.1 Hub Interface Configuration Write Transactions
18.7.9.1.2 Read Transactions from Hub Interface Targeting PCI on the PCI-X
18.7.9.1.3 Read Transactions from PCI Targeting Hub Interface
18.7.9.1.4 Write Transactions on Hub Interface – Intel
November 2007
Order Number: 300641-004US
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6300ESB ICH
Unlike address parity errors, data parity errors are not considered as severe and
transactions are aborted. The following sections describe the sequence of events when
a data parity error is detected for the following transactions:
When the Intel
write transaction to one of the Intel
6300ESB ICH:
When the Intel
Hub Interface initiated read, it:
When the Intel
completion packet from a previous memory read request on PCI, the Intel
ICH:
Interface Target
When the Intel
request, it:
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The parity errors response bit is set in the bridge control register (D28:3Eh,0)
Configuration Write Transactions
Read Transactions (inbound and outbound)
Posted Write Transaction
Does not write the data to the configuration register when parity error response is
enabled.
Sets the Detected Parity Error bit in the Primary status register (bit 15 of offset 06-
07h).
Generates NMI/SMI (depending on which is enabled) and sets the signaled system
error bit (bit 14) in the Primary status register, when the Parity Error Response
Enable bit in the command register (bit 6 of offset 04-05h) is set.
Sets the detected parity error bit in the secondary status register (bit 15 of offset
1E-1Fh).
Sets the Data parity detected bit in the secondary status register (bit 8 of offset 1E-
1Fh), when the secondary interface parity error response bit is set in the bridge
control register (bit ’0’ of offset 3E-3Fh).
Forces bad parity error with the data back to the initiator on the Hub Interface.
Sets the detected parity error bit in the primary status register (bit 15 of offset 06-
07h).
Sets the data parity detected bit in the primary status register (bit 8 of offset 06-
07h) and generates the NMI/SMI (depending on which is enabled), when the
primary interface parity error response bit is set in the command register (bit 6 of
offset 04-05h).
Forwards the bad parity with the data back to PCI.
Sets the data parity error detected bit in the status register (bit 15 of offset 06-
07h) of the target interface (PCI bridge primary).
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6300ESB ICH detects a data parity error during a Type 0 configuration
6300ESB ICH detects a read data parity error on the PCI bus from a
6300ESB ICH detects a data parity error on a Hub Interface
6300ESB ICH detects a data parity error on a Hub Interface write
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6300ESB ICH configuration spaces, the Intel
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6300ESB ICH as a Hub
Intel
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6300ESB I/O Controller Hub
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6300ESB
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