NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 656

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.6.1.4 Offset 06: PSTS—Primary Status
Intel
DS
656
Bits
02
01
0
®
Table 586. Offset 04: CMD—Command (Sheet 2 of 2)
6300ESB I/O Controller Hub
Note: For the writable bits in this register, writing a ’1’ clears the bit. Writing a ’0’ has no
Note: RASERR# will be asserted based on activity of bits 15:11, 8.
Bus Master
Device
I/O Space
Offset
Memory
(IOSE)
Name
Enable
Enable
Enable
(BME)
Space
(MSE)
effect.
28
04
Controls the ability of the Intel
master on the Hub Interface when forwarding memory
transactions from PCI-X.
When '0': the Intel
memory transactions on the PCI-X interface that target Hub
Interface.
Controls the ability of the Intel
a target to memory accesses on the Hub Interface that
address a device behind the Intel
Controls the ability of the Intel
a target to I/O transactions on the primary interface that
address a device that resides behind the Intel
®
6300ESB ICH does not respond to any
Description
®
®
®
6300ESB ICH to act as a
6300ESB ICH to respond as
6300ESB ICH to respond as
®
6300ESB ICH.
Attribute:
Function
Size:
®
6300ESB ICH.
0
Read/Write
16-bit
Order Number: 300641-004US
Reset
Value
Intel
0
0
0
®
6300ESB ICH—18
November 2007
Access
R/W
R/W
R/W