NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 26

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
26
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6300ESB I/O Controller Hub
18.7
18.8
PCI Mode in the PCI-X Interface......................................................................... 684
18.7.1 Summary of Changes ............................................................................ 684
18.7.2 Transaction Types................................................................................. 684
18.7.3 Detection of 64-Bit Environment ............................................................. 685
18.7.4 Data Bus ............................................................................................. 685
18.7.5 Write Transactions ................................................................................ 685
18.7.6 Read Transactions ................................................................................ 686
18.7.7 Transaction Termination ........................................................................ 686
18.7.8 LOCK Cycles ........................................................................................ 687
18.7.9 Error Handling...................................................................................... 687
PCI-X Interface ............................................................................................... 691
18.8.1 Command Encoding .............................................................................. 691
18.6.1.2 Offset 00: ID—Identifiers ......................................................... 654
18.6.1.3 Offset 04: CMD—Command ...................................................... 655
18.6.1.4 Offset 06: PSTS—Primary Status ............................................... 656
18.6.1.5 Offset 08: RID—Revision ID...................................................... 658
18.6.1.6 Offset 09: CC—Class Code ........................................................ 659
18.6.1.7 Offset 0C: CLS—Cache Line Size ............................................... 659
18.6.1.8 Offset 0D: PLT—Primary Latency Timer ...................................... 660
18.6.1.9 Offset 0E: HTYPE—Header Type ................................................ 660
18.6.1.10Offset 18: BNUM—Bus Numbers ................................................ 661
18.6.1.11Offset 1B: SLT—Secondary Latency Timer .................................. 661
18.6.1.12Offset 1C: IOBL—I/O Base and Limit .......................................... 662
18.6.1.13Offset 1E: SSTS—Secondary Status ........................................... 663
18.6.1.14Offset 20: MBL—Memory Base and Limit .................................... 664
18.6.1.15Offset 24: PMBL—Prefetchable Memory Base and Limit................. 665
18.6.1.16Offset 28: PMBU32—Prefetchable Memory Base Upper 32 Bits ....... 665
18.6.1.17Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32 Bits ....... 666
18.6.1.18Offset 30: IOBLU16—I/O Base and Limit Upper 16 Bits................. 666
18.6.1.19Offset 34: CAPP—Capabilities List Pointer ................................... 667
18.6.1.20Offset 3C: INTR—Interrupt Information ...................................... 667
18.6.1.21Offset 3E: BCTRL—Bridge Control .............................................. 667
18.6.1.22Offset 40: CNF—Intel
18.6.1.23Offset 42: MTT—Multi-Transaction Timer .................................... 673
18.6.1.24Offset 44: STRP—PCI Strap Status ............................................ 674
18.6.1.25Offset 50: PX_CAPID—PCI-X Capabilities Identifier ...................... 674
18.6.1.26Offset 51: PX_NXTP—Next Item Pointer ..................................... 674
18.6.1.27Offset 52: PX_SSTS—PCI-X Secondary Status ............................. 675
18.6.1.28Offset 54: PX_BSTS - PCI-X Bridge Status .................................. 676
18.6.1.29Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control .... 678
18.6.1.30Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control 678
18.6.1.31Offset E0: ACNF – Additional Intel
18.6.1.32Offset E4: PCR - PCI Compensation Register ............................... 681
18.6.1.33Offset F0: HCCR - Hub Interface Command/Control Register ......... 682
18.6.1.34Offset F8h – Offset FFh: Prefetch Control Registers ...................... 682
18.6.1.35Offset F8h: PC33 - Prefetch Control – 33 MHz ............................. 683
18.6.1.36Offset FAh: PC66 - Prefetch Control – 66 MHz ............................. 683
18.7.5.1 Posted ................................................................................... 685
18.7.5.2 Non-Posted ............................................................................ 686
18.7.5.3 Fast Back-to-Back ................................................................... 686
18.7.6.1 Prefetchable ........................................................................... 686
18.7.6.2 Delayed ................................................................................. 686
18.7.7.1 Normal Master Termination....................................................... 686
18.7.7.2 Master Abort Termination ......................................................... 686
18.7.7.3 Target Termination Received by the Intel
18.7.7.4 Target Termination Initiated by the Intel
18.7.9.1 Data Parity Errors.................................................................... 689
18.7.9.2 System Errors......................................................................... 690
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6300ESB I/O Controller Hub Configuration . 671
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6300ESB ICH Configuration .... 680
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6300ESB ICH .............. 687
6300ESB ICH.............. 687
Intel
Order Number: 300641-004US
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6300ESB ICH—Contents
November 2007