NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 143

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.10.1.4 NMI
Table 60.
5.10.1.5 STPCLK# and CPUSLP# Signals
5.10.2
5.10.2.1 Signal Differences
Table 61.
5.10.2.2 Dual Processor Power Management
November 2007
Order Number: 300641-004US
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6300ESB ICH
Non-Maskable Interrupts (NMIs) may be generated by several sources, as described in
Table
NMI Sources
The Intel
Refer to
functionality of these signals.
Dual Processor Issues
In dual processor designs, some of the processor signals are used differently than in
uniprocessor designs.
DP Signal Differences
For multiple-CPU (or Multiple-core) configurations in which more than one Stop Grant
cycle may be generated, the MCH is expected to count Stop Grant cycles and only pass
the last one through to the 6300ESB. This prevents the 6300ESB from getting out of
sync with the processor on multiple STPCLK# assertions.
SERR# goes active (either internally,
externally through SERR# signal, or
through a message from MCH)
IOCHK# goes active via SERIRQ# stream
(ISA System Error)
D30_PD_STS register (D30:F0:06h), bit 8
(Detected parity error on Hub Interface)
D30_SECSTS register (D30:F0:1Eh), bit 8
(Detected parity error on PCI by North
PCI unit)
D31F0_DEV_STS register (D31:F0:06h),
bit 8 (Detected parity error on PCI by
South PCI unit)
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
60.
Section 5.11, “Power Management (D31:F0)”
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Signal
6300ESB ICH power management logic controls these active-low signals.
Cause of NMI
Generally not used, but still supported by the Intel
Used for S1 State as well as preparation for entry to S3-S5.
Also allows for THERM# based throttling (not through ACPI control
methods). Should be connected to both processors.
Generally not used, but still supported by the Intel
May instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, offset
4E, bit 11).
May instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, offset
4E, bit 11).
Enabled by D30:F0:04h, bit 6
Enabled by D30:F0:04h, bit 6
Difference
for more information on the
Comment
Intel
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6300ESB I/O Controller Hub
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6300ESB ICH.
6300ESB ICH.
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