NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 73

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3—Intel
3.17
Table 19.
3.18
Table 20.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
AC’97 Link
AC’97 Link Signals
Universal Asynchronous Receive and
Transmit (UART0,1)
Universal Asynchronous Receive and Transmit (UART0, 1) (Sheet 1 of
2)
NOTES:
Signal Name
1. These signals are in the RESUME well, except AC_SYNC, AC_BIT_CLK, and AC_SDATA_OUT,
2. See
3. An integrated pull-down resistor on AC_BIT_CLK is enabled when either:
AC_SDIN[2:0]
UART_CLK
SIU0_RXD
SIU1_RXD
AC_BIT_CLK
SIU0_TXD
SIU1_TXD
SIU0_CTS
SIU1_CTS
AC_SDOUT
which are in the core well.
pull-down resistors are enabled on AC_SYNC, AC_BIT_CLK, and AC_SDATA_OUT.
- The ACLINK Shutoff bit in the AC’97 Global Control Register (See
“GLOB_CNT—Global Control
- Both Function 5 and Function 6 of Device 31 are disabled. Otherwise, the integrated pull-
down resistor is disabled.
AC_RST#
AC_SYNC
Name
Section 4.2, “Integrated Pull-Ups and Pull-Downs”
Type
O
I
I
I
Type
O
O
O
I
I
Input clock to the SIU. This clock is passed to the baud clock
generation logic of each UART in the SIU.
SERIAL INPUTs for UART0 and UART1: Serial data input from
device pin to the receive port.
SERIAL OUTPUT for UART0, 1: Serial data output to the
communication peripheral/modem or data set. Upon reset, the TXD
pins will be set to MARKING condition (logic ‘1’ state).
CLEAR TO SEND: Active low, this pin indicates that data may be
exchanged between the Intel
These pins have no effect on the transmitter.
NOTE: These pins could be used as Modem Status Input whose
AC’97 Reset: Master H/W reset to external Codec(s).
AC’97 Sync: 48 KHz fixed rate sample sync to the Codec(s).
AC’97 Bit Clock: 12.288 MHz serial data clock generated by the
external Codec(s). This signal has an integrated pull-down resistor
AC’97 Serial Data Out: Serial TDM data output to the Codec(s).
AC’97 Serial Data In 2:0: Serial TDM data input from the three
Codec(s). Integrated pull-down resistors, which are always enabled.
Register”) is set to ‘1’, or
condition may be tested by the processor by reading bit 4 (CTS)
of the Modem Status register (MSR). Bit 4 is the complement of
the CTS# signal. Bit 0 (DCTS) of the MSR indicates whether the
CTS# input has changed state since the previous reading of the
MSR. When the CTS bit of the MSR changes state, an interrupt
is generated when the Modem Status Interrupt is enabled.
®
Description
Description
6300ESB ICH and external interface.
for details about when the integrated
Intel
Section 13.2.8,
®
6300ESB I/O Controller Hub
3
DS
.
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