NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 464

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10.1.4
Table 355. Offset 06 - 07h: STA—Device Status Register (USB—D29:F0/F1)
10.1.5
Table 356. Offset 08h: RID—Revision Identification Register (USB—D29:F0/F1)
Intel
DS
464
15:1
10:9
Bits
Bits
Default Value:
Default Value:
4:0
7:0
13
12
11
4
8
7
6
5
®
6300ESB I/O Controller Hub
Device:
Device:
DEVSEL# Timing Status
User Definable Features
Offset:
Offset:
Received Master-Abort
Signaled Target-Abort
Fast Back-to-Back
Revision ID Value
Data Parity Error
66 MHz Capable
Status (RMA)
Status (STA)
Offset 06 - 07h: STA—Device Status Register
(USB—D29:F0/F1)
Offset 08h: RID—Revision Identification Register
(USB—D29:F0/F1)
Reserved
Reserved
Reserved
Detected
Capable
(DEVT)
29
06 - 07h
0280h
Name
29
08h
See bit description
Name
(UDF)
Reserved as ‘00b’.
0 = Software clears this bit by writing a ’1’ to the bit location.
1 = USB, as a master, generated a master-abort.
Reserved. Always read as ‘0’.
0 = Software clears this bit by writing a ’1’ to the bit location.
1 = USB function is targeted with a transaction that the
This 2-bit field defines the timing for DEVSEL# assertion.
These read only bits indicate the Intel
DEVSEL# timing when performing a positive decode. The
Intel
for USB.
Reserved as ‘0’.
Reserved as ‘1’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved.
Refer to the Intel
Update for the most up-to-date value of the Revision ID
Register.
Intel
®
6300ESB ICH generates DEVSEL# with medium timing
®
6300ESB ICH terminates with a target abort.
®
6300ESB I/O Controller Hub Specification
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0/1
Read/Write Clear
16-bit
0/1
Read-Only
8-bit
®
6300ESB ICH's
Order Number: 300641-004US
Intel
®
6300ESB ICH—10
November 2007
Access
Access
R/WC
R/WC
RO
RO
RO
RO
RO
RO
RO
RO
RO