NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 478

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10.2.2
Table 373. Offset 02 - 03h: USBSTA—USB Status Register (Sheet 1 of 2)
Intel
DS
478
15:6
Bits
Default Value:
5
4
3
®
6300ESB I/O Controller Hub
Note: This register indicates pending interrupts and various states of the Host Controller. The
Device:
Offset:
Host Controller Process
Host System Error
always resets the SOF counter so that when the Run/Stop bit is set, the Host Controller
starts over again from the frame list location pointed to by the Frame List Index (see
FRNUM Register description) rather than continuing where it stopped.
Offset 02 - 03h: USBSTA—USB Status Register
status resulting from a transaction on the serial bus is not indicated in this register.
Software sets a bit to ‘0’ in this register by writing a ‘1’ to it.
Reserved
HCHalted
29
02 - 03h
0020h
Name
Error
Reserved.
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
1 = The Host Controller has stopped executing as a result of
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
1 = The Host Controller has detected a fatal error. This
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
1 = A serious error occurred during a host system access
position.
the Run/Stop bit being set to 0, either by software or by
the Host Controller hardware (debug mode or an internal
error). Default.
position.
indicates that the Host Controller suffered a consistency
check failure while processing a Transfer Descriptor. An
example of a consistency check failure would be finding
an illegal PID field while processing the packet header
portion of the TD. When this error occurs, the Host
Controller clears the Run/Stop bit in the Command
register to prevent further schedule execution. A
hardware interrupt is generated to the system.
position.
involving the Host Controller module. In a PCI system,
conditions that set this bit to ’1’ include PCI Parity error,
PCI Master Abort, and PCI Target Abort. When this error
occurs, the Host Controller clears the Run/Stop bit in the
Command register to prevent further execution of the
scheduled TDs. A hardware interrupt is generated to the
system.
Description
Attribute:
Function:
Size:
X
Rea/Write Clear
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—10
November 2007
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