NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 98

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.2.1
Table 31.
5.2.1.1
Table 32.
Intel
DS
98
®
6300ESB I/O Controller Hub
LPC Cycle Types
The Intel
Count Interface Specification, Revision 1.0.
by the Intel
LPC Cycle Types Supported
Start Field Definition
Start Field Bit Definitions
NOTES:
NOTE: All other encodings are Reserved.
1. For memory cycles below 16M which do not target enabled FWH ranges, the Intel
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
Bits[3:0]
Encoding
Bus Master Write
Bus Master Read
ICH will perform standard LPC memory cycles. It will only attempt 8-bit transfers. When the
cycle appears on PCI as a 16-bit transfer, it will appear as two consecutive 8-bit transfers on
LPC. Likewise, when the cycle appears as a 32-bit transfer on PCI, it will appear as four
consecutive 8-bit transfers on LPC. When the cycle is not claimed by any peripheral, it will be
subsequently aborted, and the Intel
processor. This is done to maintain compatibility with ISA memory cycles where pull-up
resistors would keep the bus high when no device responds.
may be to any address. However, the 2-byte transfer must be word aligned (i.e.,with an
address where A0=0). A DWORD transfer must be DWORD aligned (i.e., with an address
where A1and A0 are both 0).
0000
0010
0011
1101
1110
1111
Memory Write
Memory Read
Cycle Type
DMA Write
DMA Read
I/O Write
I/O Read
®
6300ESB ICH implements all of the cycle types described in the Low Pin
®
Start of cycle for a generic target.
Grant for bus master 0.
Grant for bus master 1.
Start of cycle for firmware memory read cycle
Start of cycle for firmware memory write cycle
Stop/Abort: End of a cycle for a target.
6300ESB ICH.
Single: 1 byte only
Single: 1 byte only
1 byte only. The Intel
cycles into multiple 8-bit transfers.
1 byte only. The Intel
cycles into multiple 8-bit transfers.
May be 1, or 2 bytes
May be 1, or 2 bytes
May be 1, 2, or 4 bytes.
May be 1, 2, or 4 bytes.
®
6300ESB ICH will return a value of all 1s to the
1
1
®
®
6300ESB ICH breaks up 16 and 32-bit processor
6300ESB ICH breaks up 16 and 32-bit processor
2
2
Table 31
Definition
Comment
shows the cycle types supported
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007
®
6300ESB