NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 765

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20—Intel
20.1.41 Offset E4h - E7h: BFTD1—BIST FIS Transmit
November 2007
Order Number: 300641-004US
31:0
Bits
Bits
Default Value:
Default Value:
7:2
1:0
Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–
Table 700. Offset E4h - E7h: BFTD1—BIST FIS Transmit Data1 Register (SATA–
Device:
Device:
®
Offset:
Offset:
BIST FIS Transmit Data
BIST FIS Parameters
6300ESB ICH
D31:F2)
Data1 Register (SATA–D31:F2)
D31:F2)
Reserved
(Sheet 3 of 3)
31
E0h–E3h
00000000h
Name
31
E4h–E7h
00000000h
Name
1
These 6 bits form the contents of the upper 6 bits of the BIST
FIS Pattern Definition in any BIST FIS transmitted by the
Intel
contents will be used for any BIST FIS initiated on port 0 on
port 1. The specific bit definitions are:
Bit 7: T – Far End Transmit mode
Bit 6: A – Align Bypass mode
Bit 5: S – Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Primitive bit for use with Transmit mode
Reserved.
The data programmed into this register will form the contents
of the second DWord of any BIST FIS initiated by the Intel
6300ESB ICH. This register is not port specific — its contents
will be used for BIST FIS initiated on port 0 or port 1.
Although the 2nd and 3rd DWs of the BIST FIS are only
meaningful when the ‘T’ bit of the BIST FIS is set to indicate
“Far-End Transmit mode”, this register’s contents will be
transmitted as the BIST FIS 2nd DW regardless of whether or
not the ‘T’ bit is indicated in the BFCS register.
®
6300ESB ICH. This field is not port specific — its
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
2
Read/Write, Read/Write Clear
32-bit
2
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
®
Access
Access
R/W
765
DS