NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 704

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Figure 32. SIU Block Diagram
19.2
19.2.1
Table 630. Universal Asynchronous Receive And Transmit (UART0, UART1)
Intel
DS
704
®
6300ESB I/O Controller Hub
Pin Description
Universal Asynchronous Receive And Transmit
(UART0, UART1)
(Sheet 1 of 2)
UART_CLK
SIU0_RXD,
SIU1_RXD
SIU0_TXD,
SIU1_TXD
Signal Name
PORT 60/64
Emulation
Type
O
I
I
LPC I/F
Input clock to the SIU. This clock is passed to the baud clock
generation logic of each UART in the SIU.
SERIAL INPUTs for UART0 and UART1: Serial data input from
device pin to the receive port.
SERIAL OUTPUT for UART0 and UART1: Serial data output to the
communication peripheral/modem or data set. Upon reset, the TXD
pins will be set to MARKING condition (logic ‘1’ state).
APB I/F
UART0
Registers
Control
UART1
Description
Controller
SIRQ
Order Number: 300641-004US
Intel
SIU_SERIRQ
®
6300ESB ICH—19
November 2007