NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 345

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.1.37
Table 217. Offset F4: ETR1—PCI-X Extended Features Register (LPC I/F—D31:F0)
8.1.38
Table 218. Offset F8h: Manufacturer’s ID
November 2007
Order Number: 300641-004US
31:8
31:1
15:8
Bits
Bits
Default Value:
Default Value:
5:0
7:0
7
6
6
Warning:Make sure that reserved bits values are not modified to avoid indeterminate
Lockable:
Lockable:
®
Device:
Device:
Offset:
Offset:
6300ESB ICH
Trapping Disable
PXIRQ Routing
Manufacturer
Process/Dot
Offset F4: ETR1—PCI-X Extended Features
Register
(LPC I/F—D31:F0)
behavior.
Offset F8h: Manufacturer’s ID
Reserved
Reserved
Reserved
31
F4-f7h
00000000h
No
Name
31
F8h-FBh
000S 0F66
No
Name
Reserved.
Default = 0.
0 = Trapping is enabled for all access to these ports. See
1 = Disable the USB Legacy Trapping to Ports 60h and 64h
Default = 0.
0 = APIC1 boot interrupt is routed to IRQ9#. See
1 = Routes the APIC1 boot interrupt to the PIRQG# output.
Reserved.
Reserved.
0Fh = Intel
Process 859.6
Section 5.17.9, “USB Legacy Keyboard Operation”
details on USB Legacy Keyboard Operation.
when an external PCI Master is accessing these ports.
Section 5.7.3, “Boot Interrupt”
Interrupt.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
for details on Boot
0
Read/Write
32-bit
Core
0
Read-Only
32-bit
Core
Intel
®
6300ESB I/O Controller Hub
for
Access
Access
R/W
R/W
345
DS