NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 262

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 138. AC’97 Signals
Figure 25. AC-Link Protocol
Intel
DS
262
®
6300ESB I/O Controller Hub
Intel
6300ESB ICH, sampled during system reset. These signals may have weak pullups/
pulldowns on them, however this will not interfere with link operation. Intel
ICH inputs integrate weak pulldowns to prevent floating traces when a secondary and/
or tertiary codec is not attached. When the Shut Off bit in the control register is set, all
buffers will be turned off and the pins will be held in a steady state, based on these
pullups/pulldowns.
BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the
necessary clocking to support the twelve 20-bit time slots. AC-link serial data is
transitioned on each rising edge of BIT_CLK. The receiver of AC-link data samples each
serial bit on the falling edge of BIT_CLK.
When BIT_CLK makes no transitions for four consecutive PCI clocks, the Intel
6300ESB ICH assumes the primary codec is not present or not working. It sets bit 28 of
the Global Status Register (I/O offset 30h). All accesses to codec registers with this bit
set will return data of FFh to prevent system hangs.
Synchronization of all AC-link data transactions is signaled by the AC’97 controller
through the AC_SYNC signal, as shown in
serial bit clock onto the AC-link, which the AC’97 controller then qualifies with the
AC_SYNC signal to construct data frames. AC_SYNC, fixed at 48 KHz, is derived by
dividing down BIT_CLK. AC_SYNC remains high for a total duration of 16 BIT_CLKs at
the beginning of each frame. The portion of the frame where AC_SYNC is high is
defined as the tag phase. The remainder of the frame where AC_SYNC is low is defined
as the data phase. Each data bit is sampled on the falling edge of BIT_CLK.
The Intel
configuration. When multiple codecs are connected, the primary, secondary, and
tertiary codecs may be connected to any AC_SDIN line. The Intel
AC_RESET#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN 0
AC_SDIN 1
AC_SDIN 2
NOTE: Power well voltage levels are 3.3 V.
BIT_CLK
Signal Name
SDIN
SYNC
®
End of previous
Audio Frame
6300ESB ICH core well outputs may be used as strapping options for the Intel
®
6300ESB ICH has three AC_SDIN pins allowing a single, dual, or triple codec
Codec
Ready
12.288 MHz
slot(1)
Output
Output
Input
Output
Input
Input
Input
("1" = time slot contains valid PCM
data)
Tag Phase
slot(2)
81.4 nS
Type
Time Slot "Valid"
slot(12)
Bits
"0"
Resume
Core
Core
Core
Resume
Resume
Resume
Power Well
"0"
"0"
19
Slot 1
Figure
0
(48 KHz)
Master hardware reset
48 KHz fixed rate sample sync
12.288 MHz Serial data clock
Serial output data
Serial input data
Serial input data
Serial input data
20.8uS
25. The primary codec drives the
19
Slot 2
Data Phase
Description
0
19
Slot 3
Order Number: 300641-004US
®
0
Intel
6300ESB ICH does
®
6300ESB ICH—5
19
November 2007
®
Slot 12
6300ESB
®
0
®