NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 168

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.11.13 Legacy Power Management Theory of Operation
5.11.13.1Overview
5.11.13.2APM Feature Notes
5.12
5.12.1
Intel
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6300ESB I/O Controller Hub
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The Intel
legacy power management compared with previous component generations.
The scheme relies on the concept of detecting when individual subsystems are idle,
detecting when the whole system is idle, and detecting when accesses are attempted to
idle subsystems.
However, the OS is assumed to be at least APM enabled. Without APM calls, there is no
quick way to know when the system is idle between keystrokes. The Intel
ICH does not support the burst modes found in previous components.
The Intel
Control and Enable register, will generate an SMI# once per minute. The SMI handler
may check for system activity by reading the DEVACT_STS register. When none of the
system bits are set, the SMI handler may increment a software counter. When the
counter reaches a sufficient number of consecutive minutes with no activity, the SMI
handler may then put the system into a lower power state. When there is activity,
various bits in the DEVACT_STS register will be set. Software clears the bits by writing
a one to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions
on LPC or PCI. Other PCI activity may be monitored by checking the PCI interrupts.
System Management (D31:F0)
Overview of System Management Functions
The Intel
and to lower the Total Cost of Ownership (TCO) of the system. It builds on functions
that have been found in prior generations of serial interface ACPI-compatible processor
system monitor components products, such as the LM78 and LM80. Features and
functions may be augmented through external A/D converters and GPIO, as well as an
external microcontroller.
The Intel
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First Hard Coded Timer to Generate SMI# after Programmable Time.
First timeout causes SMI#. Allows for SMM-Based Recovery from OS lockup.
OS-based software agent accesses the Intel
timer.
Ability for SMM Handler to generate “TCO” interrupt to OS.
Allows for OS-based code augmentation.
Ability for OS to generate SMI#.
Call-back from OS to TCO code in SMM handler.
Second hard coded timer to generate reboot after programmable time.
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6300ESB ICH supports the following features and functions:
6300ESB ICH has a timer that, when enabled by the 1MIN_EN bit in the SMI
6300ESB ICH provides various functions to make a system easier to manage
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6300ESB ICH has a greatly simplified method for
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6300ESB ICH to periodically reload
Order Number: 300641-004US
Intel
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6300ESB ICH—5
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November 2007
6300ESB