NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 245

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 124. Block Read/Write Protocol without PEC
l
Table 125. Block Read/Write Protocol with PEC (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
I
changes slightly. The Intel
or receive the number of bytes (on reads) indicated in the DATA0 register. However, it
will not send the contents of the DATA0 register as part of the message.
2
11–18
C Mode: For Block Write, when the I
11–18
20–27
29–36
38–45
2–8
2–8
Bit
Bit
10
10
19
28
37
46
...
...
...
...
1
9
1
9
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
(Skip this step when I
set)
Acknowledge from Slave
(Skip this step when I2C_EN bit
set)
Data Byte 1 - 8 bits
Acknowledge from Slave
Data Byte 2 - 8 bits
Acknowledge from slave
Data Bytes / Slave
Acknowledges...
Data Byte N - 8 bits
Acknowledge from Slave
Stop
Block Write Protocol
Block Write Protocol
Description
Description
®
6300ESB ICH will still send the number of bytes (on writes)
2
C_En bit
2
C_EN bit is set, the format of the command
11–18
21–27
30–37
39–46
48–55
11–18
2–8
2–8
Bit
Bit
10
19
20
28
29
38
47
56
10
...
...
...
...
1
9
1
9
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Repeated Start
Slave Address - 7 bits
Read
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from slave/
Acknowledge
Data Byte N from slave - 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Block Read Protocol
Intel
®
Description
Description
6300ESB I/O Controller Hub
245
DS