NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 156

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 69.
5.11.7.3 Exiting Sleep States
Table 70.
Intel
DS
156
®
6300ESB I/O Controller Hub
Note: Interrupts might not be masked at the I/O subsystem. Some Operating Systems have
Sleep Types
Other Assumptions:
Before entering sleep state, an ACPI OS will mask all interrupts and will turn off all bus
master enable bits. For non-ACPI systems, the BIOS will mask interrupts and turn off
all bus master enable bits.
been observed to only mask interrupts inside the processor.
Sleep states (S1–S5) are exited based on Wake events. The Wake events will force the
system to a full on state (S0), although some non-critical subsystems might still be
shut off and have to be brought back manually. For example, the hard disk may be shut
off during a sleep state, and have to be enabled through a GPIO pin before it may be
used.
Upon exit from the Intel
be set.
The possible causes of Wake Events (and their restrictions) are shown in
Causes of Wake Events (Sheet 1 of 2)
RTC Alarm
NOTE: When in the S5 state due to a powerbutton override, the only wake events are Power
NOTE: PME#, RTC, GPI[0:n], and RI# will be wake events from S5 only when it was entered
•
•
•
Sleep
Type
Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor may only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
Prior to setting the SLP_EN bit, the software will turn off processor-controlled
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit will disable throttling (since S1-S5 sleep state has higher priority).
The G3 state cannot be entered through any software mechanism. The G3 state
indicates a complete loss of power.
S1
S3
S4
S5
Cause
Button, Wake SMBUs Slave Message (01h), and Hard Reset SMBus Slave Messages (03h,
04h).
through software setting the SLP_EN and SLP_TYP bits, or if there is a power failure.
The Intel
assert CPUSLP# signal. This will lower the processor’s power consumption. No
snooping is possible in this state.
The Intel
power to non-critical circuits. Power will only be retained to devices needed to
wake from this sleeping state, as well as to the memory.
The Intel
shut off the power to the memory subsystem. Only devices needed to wake from
this state should be powered.
Same power state as S4. The Intel
SLP_S5#.
®
®
®
States Can Wake
6300ESB ICH asserts the STPCLK# signal. It also has the option to
6300ESB ICH asserts SLP_S3#. The SLP_S3# signal will control the
6300ESB ICH asserts SLP_S3# and SLP_S4#. The SLP_S4# signal will
®
6300ESB ICH-controlled Sleep states, the WAK_STS bit will
S1
From
–
S5
Set RTC_EN bit in PM1_EN Register
®
Comment
6300ESB ICH asserts SLP_S3#, SLP_S4# and
How Enabled
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
Table
November 2007
70.