NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 724

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19.5.1.4.2 FIFO Polled Mode Operation
19.6
19.6.1
19.6.2
Intel
DS
724
®
6300ESB I/O Controller Hub
With the FIFOs enabled (TRFIFOE bit of FCR set to 1), setting IER[3:0] to all zeros puts
the serial port in the FIFO polled mode of operation. Since the receiver and the
transmitter are controlled separately, either one or both may be in the polled mode of
operation. In this mode, software checks receiver and transmitter status through the
LSR. As stated in the register description:
Logical Device 7 (07H): Port 60/64
Emulation
This section describes the Port 60/64 Emulation integrated into the SIU.
Feature List
Overview
The Port 60/64 Emulation Unit consists of two 8-bit I/O registers intended to preserve
values written to Port 60 and 64 thus emulating a legacy 8042 device formerly at this
legacy I/O address space. These registers may be enabled by BIOS typically in a pre-
OS environment and may be disabled during run time. These registers may be used for
8042 keyboard controller emulation but in no way support any controller or
functionality beyond a scratchpad register and interrupt generation on writes.
When enabled, this Device will positively decode 8-bit I/O accesses to address 60h and
64h.
Writes to these addresses may generate an interrupt as configured in the Logical
Device 07 Primary Interrupt Register (70h). The interrupt generated from this unit will
drive active (drives a logical 0) for one SIRQ frame. It does not require any further
action (i.e., no EOI required or status bit to clear).
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Register is written (1 to 16 characters may be written to the transmit FIFO while
servicing the interrupt) or the IIR is read.
LSR[0] is set as long as there is one byte in the receiver FIFO.
LSR[1] through LSR[4] specify which error(s) has occurred for the character at the
top of the FIFO. Character error status is handled the same way as interrupt mode.
The IIR is not affected since IER[2] = 0.
LSR[5] indicates when the transmitter FIFO needs data.
LSR[6] indicates that both the transmitter FIFO and shift register are empty.
LSR[7] indicates whether there are any errors in the receiver FIFO.
Configurable unit disable
Positive decode for I/O cycles to 60h and 64h
Read/Write Scratchpad Registers Only (sticky bits)
Interrupt on write and self-interrupt clearing
Order Number: 300641-004US
Intel
®
6300ESB ICH—19
November 2007