NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 666

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.6.1.17Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32
18.6.1.18Offset 30: IOBLU16—I/O Base and Limit Upper 16 Bits
Intel
DS
666
31:0
31:1
15:0
Bits
Bits
0
6
0
®
Table 600. Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32 Bits
Table 601. Offset 30: IOBLU16—I/O Base and Limit Upper 16 Bits
6300ESB I/O Controller Hub
Note: This defines the upper 32 bits of the prefetchable address limit register.
Note: Since I/O is limited to 64 Kbytes, this register is reserved and not used.
Limit Upper
Bits (IOBH)
Prefetchabl
Bits (IOLH)
Device
Device
e Memory
Offset
Offset
I/O Base
I/O Limit
High 16
High 16
(PMLU)
Portion
Name
Name
Bits
28
2C
28
30
All bits are read/writable - the Intel
full 64-bit addressing.
NOTE: The upper 32 bits should not be used to determine the
Reserved.
Reserved.
prefetch region. The Intel
only 32-bit downstream cycles, so the upper 32 bits of
the prefetch region are ignored. Prefetch regions are
limited to a single 4 Gbyte boundary. The upper 32
bits of the prefetch region cannot be used to extend
this region. The Intel
upstream cycles, although the upper 32 bits are not
used to determined the destination if the target lies
within the Intel
®
Description
Description
6300ESB ICH
®
6300ESB ICH supports 64-bit
®
6300ESB ICH supports
®
6300ESB ICH supports
.
Attribute:
Attribute:
Function
Function
Size:
Size:
0
Read/Write
32-bit
0
Read-Only
32-bit
00000000h
Order Number: 300641-004US
Reset
Value
Reset
Value
0000h
0000h
Intel
®
6300ESB ICH—18
November 2007
Access
Access
R/W
RO
RO