NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 496

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11.1.19 Offset 59h: Next Item Pointer #2
Table 397. Offset 59h: Next Item Pointer #2
11.1.20 Offset 5Ah - 5Bh: Debug Port Base Offset
Table 398. Offset 5Ah - 5Bh: Debug Port Base Offset
11.1.21 Offset 60h: Serial Bus Release Number
Table 399. Offset 60h: Serial Bus Release Number
11.1.22 Offset 61h: Frame Length Adjustment
Intel
DS
496
15:1
12:0
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
7:0
3
®
6300ESB I/O Controller Hub
Note: This feature is used to adjust any offset from the clock source that generates the clock
Device:
Device:
Device:
Offset:
Offset:
Offset:
Next Item Pointer #2
Debug Port Offset
BAR Number
that drives the SOF counter. When a new value is written into these six bits, the length
of the frame is adjusted. Its initial programmed value is system dependent based on
the accuracy of hardware USB clock and is initialized by system BIOS. This register
should only be modified when the HChalted bit in the USBSTS register is a ‘1’. Changing
value of this register while the host controller is operating yields undefined results. It
29
59h
00h
Name
29
5Ah - 5Bh
2080h
Name
29
60h
20h
Name
This register is hardwired to 00h which indicates there are no
more capability structures in this function.
This field is hardwired to 20h to indicate the memory BAR
begins at offset 20h in the EHCI configuration space.
This field is hardwired to 080h to indicate that the Debug Port
registers begin at offset 80h in the EHCI memory range.
A value of 20h indicates that this controller follows the USB
Specification rev. 2.0.
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
7
Read-Only
8-bit
7
Read-Only
16-bit
7
Read-Only
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
Access
Access
RO
RO
RO