NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 374

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 258. Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection
Intel
DS
374
10:8
Bits
Default Value:
7:0
16
15
14
13
12
11
®
6300ESB I/O Controller Hub
Device:
Offset:
Interrupt Input Pin
Destination Mode
Delivery Status
Delivery Mode
Trigger Mode
Remote IRR
Table
(Sheet 2 of 2)
Polarity
31
10h-11h (vector 0)
through
3E-3Fh (vector 23)
Bit 16-1, Bits[15:12]=0.
All other bits undefined
Name
Vector
Mask
0 = Not masked: An edge or level on this interrupt pin results
1 = Masked: Interrupts are not delivered nor held pending.
This field indicates the type of signal on the interrupt pin that
triggers an interrupt.
0 = Edge triggered.
1 = Level triggered.
This bit is used for level triggered interrupts (in Fixed or
Lowest priority Delivery Modes only); its meaning is
undefined for edge triggered interrupts. For level triggered
interrupts, this bit is set if the I/O APIC successfully sends the
level interrupt vector in this entry. This bit is never set for
SMI, NMI, INT or ExtINT delivery modes.
This bit specifies the polarity of each interrupt signal
connected to the interrupt pins.
0 = Active high.
1 = Active low.
This field contains the current status of the delivery of this
interrupt. Writes to this bit have no effect.
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, but delivery is held
This field determines the interpretation of the Destination
field.
0 = Physical. Destination APIC ID is identified by bits [59:56].
1 = Logical. Destinations are identified by matching bit
This field specifies how the APICs listed in the destination
field should act upon reception of this signal. Certain Delivery
Modes will only operate as intended when used in conjunction
with a specific trigger mode. These encodings are listed in the
note below:
This field contains the interrupt vector for this interrupt.
Values range between 10h and FEh.
in the delivery of the interrupt to the destination.
Setting this bit after the interrupt is accepted by a local
APIC has no effect on that interrupt. This behavior is
identical to the device withdrawing the interrupt before it
is posted to the processor. It is software's responsibility
to deal with the case where the mask bit is set after the
interrupt message has been accepted by a local APIC unit
but before the interrupt is dispensed to the processor.
up due to the APIC bus being busy or the inability of the
receiving APIC unit to accept the interrupt at this time.
[63:56] with the Logical Destination in the Destination
Format Register and Logical Destination Register in each
Local APIC.
Description
Attribute:
Function:
Size:
0
Read/Write
64-bit (accessed as two 32 bit
quantities)
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO