NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 162

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.11.10 ALT Access Mode
Intel
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6300ESB I/O Controller Hub
Note: The THRMTRIP# pin must be glitch free.
When the processor is running extremely hot and is heating up, it is possible (although
very unlikely) that components around it, such as the Intel
longer executing cycles properly. Therefore, when THRMTRIP# fires and the Intel
6300ESB ICH is relying on state machine logic to perform the power down, the state
machine may not be working and the system will not power down.
The Intel
A Processor Thermal trip event will:
Before entering a low power state, several registers from powered down parts may
need to be saved. In the majority of cases, this is not an issue, as registers have read
and write paths. However, several of the ISA compatible registers are either read only
or write only. To get data out of write-only registers, and to restore data into read-only
registers, the Intel
When the ALT access mode is entered and exited after reading the registers of the
Intel
following steps listed below may cause problems:
After getting control in step #3, when the OS does not reprogram the system timer
again the timer ticks may be happening faster than expected. For example DOS and its
associated software assume that the system timer is running at 54.6 ms and as a result
the timeouts in the software may be happening faster than expected.
For some other OSs, such as DOS, the BIOS should restore the timer back to 54.6 ms
before passing control to the OS. When the BIOS is entering ALT access mode before
entering the suspend state it is not necessary to restore the timer contents after the
exit from ALT access mode.
1. At boot (PXPCIRST# low), THRMTRIP# ignored.
2. After power-up (PXPCIRST# high), when THRMTRIP# sampled active, SLP_S3#,
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay
4. When S5 state reached, go to step #1, otherwise stay here. When the Intel
1. BIOS enters ALT access mode for reading the Intel
2. BIOS exits ALT access mode.
3. BIOS continues through the execution of other needed steps and passes control to
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SLP_S4#, and SLP_S5# fire, and normal sequence of sleep machine starts.
active, even when THRMTRIP# is now inactive. This is the equivalent of “latching”
the thermal trip event.
6300ESB ICH never reaches S5, the Intel
is cycled.
Set the AFTERG3_EN bit
Clear the PWRBTN_STS bit
Clear all the GPE0_EN and GPE1_EN register bits
Clear the SMB_WAK_STS bit only when SMB_WAK_STS was set due to SMBus slave
receiving message and not set due to SMBAlert.
registers.
the OS.
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6300ESB ICH timer (8254), the timer starts counting faster (13.5 ms). The
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6300ESB ICH will follow this flow for THRMTRIP#.
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6300ESB ICH implements an ALT access mode.
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6300ESB ICH will not reboot until power
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6300ESB ICH timer related
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6300ESB ICH, are no
Order Number: 300641-004US
Intel
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6300ESB ICH—5
November 2007
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