NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 540

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12.2.5
12.2.6
Intel
DS
540
Bits
Bits
Default Value:
Default Value:
7:0
7:0
®
Table 444. Offset 05h: HST_D0—Data 0 Register
Table 445. Offset 06h: HST_D1—Data 1 Register
6300ESB I/O Controller Hub
Device:
Device:
Offset:
Offset:
DATA0/COUNT
Offset 05h: HST_D0—Data 0 Register
Offset 06h: HST_D1—Data 1 Register
DATA1
31
05h
00h
Name
31
06h
00h
Name
This field contains the eight-bit data sent in the DATA0 field of
the SMBus protocol. For block write commands, this register
reflects the number of bytes to transfer. This register should
be programmed to a value between 1 and 32 for block
counts. A count of 0 or a count above 32 will result in
unpredictable behavior. The host controller does not check or
log illegal block counts.
This eight-bit register is transmitted in the DATA1 field of the
SMBus protocol during the execution of any command.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
3
Read/Write
8-bit
3
Read/Write
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—12
November 2007
Access
Access
R/W
R/W