NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 109

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.4.7
November 2007
Order Number: 300641-004US
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Note: Indicating a ‘0000b’ or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit
Note: The host will stop the transfer on the LPC bus as indicated, fill the upper byte with
6300ESB ICH
The DMA agent uses a SYNC encoding on each byte of data being transferred, which
indicates to the Intel
more bytes are requested. To indicate the last byte of transfer, the peripheral uses a
SYNC value of ‘0000b’ (ready with no error), or ‘1010b’ (ready with error). These
encodings tell the Intel
a DMA read (Intel
piece of data transferred on a DMA write (peripheral to the Intel
When the Intel
transfer after this byte and deasserts the DMA request to the 8237. Therefore, when
the Intel
after one byte by indicating a SYNC value of ‘0000b’ or ‘1010b’. The Intel
ICH will not attempt to transfer the second byte, and will deassert the DMA request
internally. This also holds true for any byte in a 32 bit transfer. This allows the
peripheral, therefore, to terminate a DMA burst.
When the peripheral indicates a ‘0000b’ or ‘1010b’ SYNC pattern on the last byte of the
indicated size, then the Intel
8237 since it does not need to end the transfer.
When the peripheral wishes to keep the DMA request active, it uses a SYNC value of
‘1001b’ (ready plus more data). This tells the 8237 that more data bytes are requested
after the current byte has been transferred, so the Intel
DMA request active to the 8237. Therefore, on an 8-bit transfer size, when the
peripheral indicates a SYNC value of ‘1001b’ to the Intel
be transferred and the DMA request will remain active to the 8237. At a later time, the
Intel
etc. combination to initiate another transfer to the peripheral.
The peripheral must not assume that the next START indication from the Intel
6300ESB ICH is another grant to the peripheral when it had indicated a SYNC value of
‘1001b’. On a single mode DMA device, the 8237 will rearbitrate after every transfer.
Only demand mode DMA devices may be ensured that they will receive the next START
indication from the Intel
channel (first byte of a 16 bit transfer) is an error condition.
random data on DMA writes (peripheral to memory), and indicate to the 8237 that the
DMA transfer occurred, incrementing the 8237’s address and decrementing its byte
count.
SYNC Field/LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and
are ended through a SYNC field during the DMA transfer, the peripheral must obey the
following rule when initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a deassertion is
indicated through the SYNC field. This is needed to allow the 8237, which typically runs
off a much slower internal clock, to see a message deasserted before it is re-asserted
so that it may arbitrate to the next agent.
Under default operation, the host will only perform 8-bit transfers on 8-bit channels
and 16-bit transfers on 16 bit channels.
The method by which this communication between host and peripheral through system
BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC
peripheral are motherboard devices, no “plug-n-play” registry is required.
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6300ESB ICH will then come back with another START
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6300ESB ICH indicated a 16 bit transfer, the peripheral may end the transfer
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6300ESB ICH sees one of these two encodings, it ends the DMA
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6300ESB ICH to peripheral), or the byte which follows is the last
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6300ESB ICH whether this is the last byte of transfer or when
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6300ESB ICH that this is the last piece of data transferred on
6300ESB ICH.
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6300ESB ICH will only deassert the DMA request to the
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6300ESB ICH will keep the
6300ESB ICH, the data will
Intel
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CYCTYPE
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6300ESB I/O Controller Hub
6300ESB ICH).
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CHANNEL
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6300ESB
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SIZE
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