NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 428

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 316. Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output
Intel
DS
428
21:1
15:0
Bits
Default Value:
23
6
®
6300ESB I/O Controller Hub
Lockable:
Device:
Offset:
GP_LVL[n]
GP_LVL[n]
Register
Reserved
31
GPIOBASE +0Ch
1B3F0000h
No
Name
These bits may be updated by software to drive a high or low
value on the output pin. These bits correspond to GPIO that
are in the core well, and will be reset to their default values
by PXPCIRST#.
0 = Low
1 = High
These bits may be updated by software to drive a high or low
value on the output pin. These bits correspond to GPIO that
are in the core well, and will be reset to their default values
by PXPCIRST#.
0 = Low
1 = High
Reserved. These bits are not needed as the level of general
inputs can be read through the GPE0_STS and
ALT_GP_SMI_STS registers. See
Section 8.8.3.12
Power Well:
Description
Attribute:
Function:
Size:
Section 8.8.3.7
0
Read/Write
32-bit
See bit descriptions
and
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W