NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 617

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16—Intel
16.3
Table 535. WDT Interface
16.4
16.4.1
Table 536. Configuration Registers (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Signal Descriptions
The following signals are driven from the WDT.
Device 29: Function 4 Configuration
Registers
Configuration Registers
NOTE: Refer to the Intel
WDT_TOUT#/
(Internal only
00-01h
02-03h
04-05h
06-07h
10-13h
Offset
GPIO[32]
WDT_INT
0Ah
0Bh
08h
09h
0Eh
Signal
signal)
date value of the Revision ID register.
Vendor ID
Device ID
Command Register (COM)
Device Status Register (DS)
Revision ID Register (RID)
Programming Interface Register (PI)
Sub Class Code Register (SCC)
Base Class Code Register (BCC)
Header Type Register (HEDT)
Base Address Register (BAR)
Type
®
O
O
6300ESB I/O Controller Hub Specification Update for the most up-to-
Register
Watchdog Timer Timeout: The WDT_TOUT# signal is driven
low from the Intel
signal is driven low when the main 35-bit down-counter
reaches zero during the second stage. The WDT_TOUT_CNF bit
in the Configuration register determines if the output is to
change from the previous state when another timeout occurs,
or WDT_OUT# is driven low until the system is reset or power
is cycled.
Driven active to indicate the second stage of the WDT has
overflowed. This signal will toggle states for each overflow in
periodic mode. In non-periodic mode, this signal will go active
low and remain in this state until a system reset or power
cycle.
This signal is muxed with GPIO[32].
Interrupt: The WDT_INT# is an internal signal that is used to
generate an interrupt when the first stage has been allowed to
reach zero. The WDT is capable of generating SCI, SMI, and
IRQ (APIC 1, INT 10) based interrupts. Interrupts are not
generated when WDT_TOUT_CNF is set to change output after
every timeout (See Configuration Register). The WDT INT#
signal is an active low interrupt.
®
Name and Description
6300ESB ICH to an external pin. The
00000000h
See
Default
25ABh
8086h
0000h
0280h
00h
80h
08h
00h
NOTE:
Intel
®
6300ESB I/O Controller Hub
Read/Write Clear
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Type
617
DS