NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 389

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.8.1.5
Table 276. Offset B8h - BBh: GPI_ROUT—GPI Routing Control Register (PM—
November 2007
Order Number: 300641-004US
31:2
Bits
Default Value:
1:0
Lockable:
®
Device:
GPI[15] through GPI[1]
Offset:
6300ESB ICH
GPI0 Route
Offset B8h - BBh: GPI_ROUT—GPI Routing Control
Register
(PM—D31:F0)
D31:F0)
31
B8h - BBh
0000h
No
Name
See bits 1:0 for description.
GPIO[15:0] may be routed to cause an SMI or SCI when the
GPI[n]_STS bit is set. When the GPIO is not set to an input,
this field has no effect.
When the system is in an S1-S5 state and if the GPE0_EN bit
is also set, the GPI may cause a Wake event, even if the GPI
is NOT routed to cause an SMI# or SCI. Exception: If the
system is in S5 state due to a powerbutton override, then the
GPIs will not cause wake events,
00 = No effect.
01 = SMI# (when corresponding ALT_GP_SMI_EN bit is also
set)
10 = SCI (when corresponding GPE0_EN bit is also set)
11 = Reserved
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
Resume
Intel
®
6300ESB I/O Controller Hub
Access
R/W
389
DS