NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 750

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20.1.20 IDE_TIMS—Secondary IDE Timing Register
20.1.21 Offset 44h: SIDETIM—Slave IDE Timing Register
Intel
DS
750
Bits
Default Value:
7:6
5:4
3:2
1:0
®
Table 680. Offset 44h: SIDETIM—Slave IDE Timing Register (SATA–D31:F2)
6300ESB I/O Controller Hub
Note: See the above register description for “Primary IDE Timing Register.”
Device:
Recovery Time (SRCT1)
Offset:
Recovery Time (PRCT1)
Primary Drive 1 IORDY
Sample Point (PISP1)
IORDY Sample Point
Secondary Drive 1
Secondary Drive 1
Primary Drive 1
(SATA–D31:F2)
(SATA–D31:F2)
(SISP1)
31
44h
00h
Name
Determines the number of PCI clocks between IDE IOR#/
IOW# assertion and the first IORDY sample point, when the
access is to drive 1 data port and bit 14 of the IDE timing
register for secondary is set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Determines the minimum number of PCI clocks between the
last IORDY sample point and the IOR#/IOW# strobe of the
next cycle, when the access is to drive 1 data port and bit 14
of the IDE timing register for secondary is set.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Determines the number of PCI clocks between IOR#/IOW#
assertion and the first IORDY sample point, when the access
is to drive 1 data port and bit 14 of the IDE timing register for
primary is set.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Determines the minimum number of PCI clocks between the
last IORDY sample point and the IOR#/IOW# strobe of the
next cycle, when the access is to drive 1 data port and bit 14
of the IDE timing register for primary is set.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Description
Attribute:
Function:
Size:
2
Read/Write
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—20
November 2007
Access
R/W
R/W
R/W
R/W