NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 657

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
November 2007
Order Number: 300641-004US
10:0
03:0
Bits
15
14
13
12
11
08
07
06
05
04
9
Table 587. Offset 06: PSTS—Primary Status
Abort (STA)
Abort (RTA)
Parity Error
Error (SSE)
®
Data Parity
Fast Back-
Device
DEVSEL#
Offset
Detected
Detected
Reserved
Reserved
Received
Received
Signaled
Signaled
Capabil-
ities List
Capable
Capable
to-Back
System
66 MHz
6300ESB ICH
(CAPE)
Master
Timing
Enable
Name
(RMA)
Target
Target
(DPD)
(DVT)
(DPE)
Abort
(FBC)
(C66)
Error
28
06
When set to 1, this bit indicates that the Intel
detected an address parity, data parity, error on the Hub
Interface. This bit gets set even when the Parity Error
Response bit (bit 6 of the command register) is not set. Note
that each bridge sets this bit, regardless of address.
NOTE: The Hub Interface Parity Unsupported bit
This bit is set to ’1’ when the SERR# is reported to the Hub
Interface through the NMI/SMI# assertion when enabled.
This bit is set whenever the Intel
master on the Hub Interface and receives a completion
packet with master abort status.
This bit is set whenever the Intel
master on the Hub Interface and receives a completion
packet with target abort status.
This bit is set whenever the Intel
completion packet with target abort status.
These bits have no meaning on the Hub Interface. Fast
decode timing is reported.
This bit is set when the Intel
completion packet from the Hub Interface from a previous
request and detects a parity error, and the Parity Error
Response bit in the Command Register (offset 04h, bit 6) is
set.
This bit has no meaning on the Hub Interface.
Reserved.
This bit has no meaning on the Hub Interface but is set to be
true in case of any software dependencies on bandwidth
calculations.
Indicates that the Intel
capabilities pointer in the bridge. Offset 34h indicates the
offset for the first entry in the linked list of capabilities.
Reserved.
(D30:F0:40h:bit 20) must be cleared for the PER bit
to have any effect.
®
Description
6300ESB ICH contains the
®
6300ESB ICH receives a
®
®
®
6300ESB ICH generates a
6300ESB ICH is acting as
6300ESB ICH is acting as
Attribute:
Function
Size:
®
6300ESB ICH
0
Read/Write Clear
16-bit
Intel
®
Reset
Value
6300ESB I/O Controller Hub
00
0h
0
0
0
0
0
0
0
0
1
1
Access
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
RO
RO
RO
RO
RO
RO
657
DS