NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 522

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
11.2.3
11.2.3.1 Offset 00h: Control/Status Register
Table 421. Offset 00h: Control/Status Register (Sheet 1 of 3)
27:1
Bits
Default Value:
November 2007
Order Number: 300641-004US
31
30
29
28
7
Device:
®
Offset:
6300ESB ICH
ENABLED_CNT
OWNER_CNT
Reserved.
USB 2.0-Based Debug Port Register
The Debug Port’s registers are located in the same memory area, defined by the Base
Address Register (BAR) as the standard EHCI registers. The base offset for the debug
port registers is declared in the Debug Port Base Offset Capability Register at
Configuration offset 5Ah. The specific EHCI port that supports this debug capability is
indicated by a 4-bit field (bits 20-23) in the HCSPARAMS register of the EHCI controller.
The map of the Debug Port registers is shown below. Each register is defined
individually.
Reserved
Reserved
NOTES:
Name
29
00h
0000h
Offset
1. All of these registers are implemented in the core well and reset by PXPCIRST#, EHC
2. The hardware associated with this register provides no checks to ensure that software
00h
04h
08h
0Ch
10h
HCRESET, and a EHC D3-to-D0 transition
programs the interface correctly. How the hardware behaves when programmed illegally is
undefined.
Control/Status Register
USB PIDs
Data Buffer (Bytes 3:0)
Data Buffer (Bytes 7:4)
Config Register
Reserved.
When software writes a ’1’ to this bit, the ownership of the
debug port is forced to the EHCI controller (i.e., immediately
taken away from the companion Classic USB Host Controller).
When the port was already owned by the EHCI controller,
setting this bit has no effect. This bit overrides all of the
ownership-related bits in the standard EHCI registers. Reset
default is ’0’.
Reserved.
This bit = ’1’ when the debug port is enabled for operation.
Software may clear this by writing a ’0’ to it. The hardware
clears the bit for the same conditions where the Port Enable/
Disable Change bit (in the PORTSC register) is set. Software
may directly set this bit when the port is already enabled in
the associated Port Status and Control register (this is
enforced by the hardware). Reset default is ’0’.
Reserved.
Register
Description
Attribute:
Function:
.
Size:
7
Read/Write
32-bit
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Intel
®
6300ESB I/O Controller Hub
Type
Access
R/W
522
DS